Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array)

• Main Authors: Nia Gella Augoestien, Ryan Aditya
• Format: Article
• Language: Indonesian
• Published: Universitas Gadjah Mada 2019-04-01
• Series: IJEIS (Indonesian Journal of Electronics and Instrumentation Systems)
• Subjects: High speed computation; single clock processing; Low latency
• Online Access: https://jurnal.ugm.ac.id/ijeis/article/view/43906

Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process. When CRC is implemented using embedded software or processor, CRC requires many clock cycles. If CRC Generator implemented in special dedicated hardware, computational time reduced so that it can be met the high speed system communication requirement. This paper propose the design and implementation of CRC generator on FPGA that capable to minimaze computational time. The method is to reduce calculation latency by separating the coefficients of certain digits and calculating directly the result of  polinomial key modulo. CRC Generator in this paper was implemented on Xilinx Spartan®-6 Series (XC6LX16-CS324). The modeling results have succeeded  to finish computation on 1 clock cycle. Hardware eficiency is achieved 0.38 Gbps/Slice, while the throughput is 3,758 Gbps.