An 8-Bit ROM-Free AES Design for Low-Cost Applications

We have presented a memory-less design of the advanced encryption standard (AES) with 8-bit data path for applications of wireless communications. The design uses the minimal 160 clock cycles to process a 128-bit data block. For achieving the requirements of low area cost and high performance, new d...

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Main Authors: Ming-Chih Chen, Wei-Ting Li
Format: Article
Language:English
Published: Hindawi Limited 2013-01-01
Series:Mathematical Problems in Engineering
Online Access:http://dx.doi.org/10.1155/2013/696717
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spelling doaj-93555126d3d14a1d9403c7625e0d092d2020-11-24T21:00:35ZengHindawi LimitedMathematical Problems in Engineering1024-123X1563-51472013-01-01201310.1155/2013/696717696717An 8-Bit ROM-Free AES Design for Low-Cost ApplicationsMing-Chih Chen0Wei-Ting Li1Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung City 811, TaiwanDepartment of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung City 811, TaiwanWe have presented a memory-less design of the advanced encryption standard (AES) with 8-bit data path for applications of wireless communications. The design uses the minimal 160 clock cycles to process a 128-bit data block. For achieving the requirements of low area cost and high performance, new design methods are used to optimize the MixColumns (MC) and Inverse MixColumns (IMC) and ShiftRows (SR) and Inverse ShiftRows (ISR) transformations. Our methods can efficiently reduce the required clock cycles, critical path delays, and area costs of these transformations compared with previous designs. In chip realization, our design with both encryption and decryption abilities has a 29% area increase but achieves 4.85 times improvement in throughput/area compared with the best 8-bit AES design reported before. For encryption only, our AES occupies 3.5 k gates with the critical delay of 12.5 ns and achieves a throughput of 64 Mbps which is the best design compared with previous encryption-only designs.http://dx.doi.org/10.1155/2013/696717
collection DOAJ
language English
format Article
sources DOAJ
author Ming-Chih Chen
Wei-Ting Li
spellingShingle Ming-Chih Chen
Wei-Ting Li
An 8-Bit ROM-Free AES Design for Low-Cost Applications
Mathematical Problems in Engineering
author_facet Ming-Chih Chen
Wei-Ting Li
author_sort Ming-Chih Chen
title An 8-Bit ROM-Free AES Design for Low-Cost Applications
title_short An 8-Bit ROM-Free AES Design for Low-Cost Applications
title_full An 8-Bit ROM-Free AES Design for Low-Cost Applications
title_fullStr An 8-Bit ROM-Free AES Design for Low-Cost Applications
title_full_unstemmed An 8-Bit ROM-Free AES Design for Low-Cost Applications
title_sort 8-bit rom-free aes design for low-cost applications
publisher Hindawi Limited
series Mathematical Problems in Engineering
issn 1024-123X
1563-5147
publishDate 2013-01-01
description We have presented a memory-less design of the advanced encryption standard (AES) with 8-bit data path for applications of wireless communications. The design uses the minimal 160 clock cycles to process a 128-bit data block. For achieving the requirements of low area cost and high performance, new design methods are used to optimize the MixColumns (MC) and Inverse MixColumns (IMC) and ShiftRows (SR) and Inverse ShiftRows (ISR) transformations. Our methods can efficiently reduce the required clock cycles, critical path delays, and area costs of these transformations compared with previous designs. In chip realization, our design with both encryption and decryption abilities has a 29% area increase but achieves 4.85 times improvement in throughput/area compared with the best 8-bit AES design reported before. For encryption only, our AES occupies 3.5 k gates with the critical delay of 12.5 ns and achieves a throughput of 64 Mbps which is the best design compared with previous encryption-only designs.
url http://dx.doi.org/10.1155/2013/696717
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