A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

<p/> <p>Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstr...

Full description

Bibliographic Details
Main Authors: Carreira Alex, Fox Trevor W, Turner Laurence E
Format: Article
Language:English
Published: SpringerOpen 2003-01-01
Series:EURASIP Journal on Advances in Signal Processing
Subjects:
placement
mapping
FIR filter
PCLS
bit serial
JBits
Online Access:http://dx.doi.org/10.1155/S1110865703301015

Internet

http://dx.doi.org/10.1155/S1110865703301015

Similar Items