Design and implement of a 1 GHz to 6 GHz phase interpolator with wideband and high-linearity

• Main Authors: Liu Ying, Tian Ze, Lv Junsheng, Shao Gang, Hu Shufan, Li Jia
• Format: Article
• Language: zho
• Published: National Computer System Engineering Research Institute of China 2020-04-01
• Series: Dianzi Jishu Yingyong
• Subjects: phase interpolator; clock and data recovery circuit; linearity
• Online Access: http://www.chinaaet.com/article/3000117619

In order to enhance the performances of clock and data recovery circuit(CDR) in the high speed multichannel serial transceiver system, a novel phase interpolator(PI) circuit used in CDR has been proposed in the paper. It adopts four groups of differential signal and DAC to act on common load resistance, generates complementary thermometer code through digital filter to control DAC output current, realizes phase weight allocation for differential input clock to make 128 times interpolated, and optimizes the differential signal by input stage four phase correction circuit and duty cycle adjustment circuit. This chip is fabricated in 40 nm CMOS process, the simulation results show that PI has good linearity from 1 GHz to 6 GHz, and DNL is no more than 1.4 LSB, INL is no more than 1.5 LSB, and has been successfully applied to a variety of high speed SerDes.