POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS
A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and...
| Main Authors: | , |
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| Format: | Article |
| Language: | Russian |
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The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2016-10-01
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| Series: | Informatika |
| Online Access: | https://inf.grid.by/jour/article/view/112 |
| Summary: | A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis. |
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| ISSN: | 1816-0301 |