A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neur...

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Main Authors:	Khaled Ben Khalifa, Ahmed Ghazi Blaiech, Mohamed Hédi Bedoui
Format:	Article
Language:	English
Published:	Hindawi Limited 2019-01-01
Series:	Computational Intelligence and Neuroscience
Online Access:	http://dx.doi.org/10.1155/2019/8212867

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spelling	doaj-8d1af0710611430485f2bc6a9c1a67352020-11-25T01:45:00ZengHindawi LimitedComputational Intelligence and Neuroscience1687-52651687-52732019-01-01201910.1155/2019/82128678212867A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural NetworkKhaled Ben Khalifa0Ahmed Ghazi Blaiech1Mohamed Hédi Bedoui2University of Sousse, Higher Institute of Applied Sciences and Technology of Sousse, Sousse, TunisiaUniversity of Sousse, Higher Institute of Applied Sciences and Technology of Sousse, Sousse, TunisiaUniversity of Monastir, LR12ES06-Laboratory of Technology and Medical Imaging, Monastir, TunisiaIn this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.http://dx.doi.org/10.1155/2019/8212867
collection	DOAJ
language	English
format	Article
sources	DOAJ
author	Khaled Ben Khalifa Ahmed Ghazi Blaiech Mohamed Hédi Bedoui
spellingShingle	Khaled Ben Khalifa Ahmed Ghazi Blaiech Mohamed Hédi Bedoui A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network Computational Intelligence and Neuroscience
author_facet	Khaled Ben Khalifa Ahmed Ghazi Blaiech Mohamed Hédi Bedoui
author_sort	Khaled Ben Khalifa
title	A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network
title_short	A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network
title_full	A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network
title_fullStr	A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network
title_full_unstemmed	A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network
title_sort	novel hardware systolic architecture of a self-organizing map neural network
publisher	Hindawi Limited
series	Computational Intelligence and Neuroscience
issn	1687-5265 1687-5273
publishDate	2019-01-01
description	In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.
url	http://dx.doi.org/10.1155/2019/8212867
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A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

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