Редукція та оптимальна швидкодія ациклічних суматорів бінарних кодів

Редукція та оптимальна швидкодія ациклічних суматорів бінарних кодів

Проведеними дослідженнями встановлена перспектива збільшення продуктивності обчислювальних компонентів, зокрема комбінаційних суматорів, на основі використання принципів обчислення цифрових сигналів ациклічної моделі. Застосування ациклічної моделі розраховано на: – процес послідовного (для молодш...

Full description

Bibliographic Details
Main Authors:	Mykhailo Solomko, Petro Tadeyev, Yaroslav Zubyk, Olena Hladka
Format:	Article
Language:	English
Published:	PC Technology Center 2019-02-01
Series:	Eastern-European Journal of Enterprise Technologies
Subjects:	acyclic model of addition of binary codes prefix model ling adder kogge-stone adder han-carlson adder
Online Access:	http://journals.uran.ua/eejet/article/view/157150

Similar Items

Оптимізація ациклічних суматорів бінарних кодів
by: Mykhailo Solomko
Published: (2018-01-01)

Optimal performance of 16-bit acyclic adders of binary codes
by: Mykhailo Solomko, et al.
Published: (2019-06-01)

DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER
by: Rambabu Nusullapalli, et al.
Published: (2018-12-01)

Pipelined Two-Operand Modular Adders
by: M. Czyzak, et al.
Published: (2015-04-01)

DESIGN OF A LOW LATENCY ASYNCHRONOUS ADDER USING EARLY COMPLETION DETECTION
by: KOK KEONG LAI, et al.
Published: (2014-12-01)

Fast Mux-based Adder with Low Delay and Low PDP
by: H. Tavakolaee, et al.
Published: (2019-07-01)

A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
by: Muhammad Ali Akbar, et al.
Published: (2021-07-01)

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis
by: Mehedi Hasan, et al.
Published: (2021-05-01)

Synthesis of 64 bit Energy Efficient and Reconfigurable Adder
by: Dara, chandra babu
Published: (2009)

Implementation of Pipelined Bit-parallel Adders
by: Wei, Lan
Published: (2003)

Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications
by: T. Suguna, et al.
Published: (2020-04-01)

Dual-field modular multiplier using Kogge-Stone adder
by: Yang Danyang, et al.
Published: (2019-08-01)

Binary adders
by: Lynch, Thomas Walker
Published: (2011)

EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS
by: S. D. Thabah, et al.
Published: (2017-06-01)

CNTFET BASED NOVEL 14T ADDER CELL FOR LOW POWER COMPUTATION
by: Balaji Ramakrishna S, et al.
Published: (2017-10-01)

CNTFET BASED NOVEL 14T ADDER CELL FOR LOW POWER COMPUTATION
by: Balaji Ramakrishna S, et al.
Published: (2017-10-01)

IMPROVING SYSTEM PERFORMANCE BY USING PREFIX ADDERS IN RNS
by: M. Augusta Angel, et al.
Published: (2016-07-01)

RECONSTRUCTION OF EXISTING LIVESTOCK FEED PRODUCTION PLANTS BY ADDING A HYDRAULIC ADDER
by: D. Kiš, et al.
Published: (2007-06-01)

Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions
by: Padmanabhan Balasubramanian, et al.
Published: (2018-12-01)

Ambulatory electrocardiography and serum cardiac troponin I measurement in 21 dogs envenomated by the European adder (Vipera berus)
by: Hannah J. Harjen, et al.
Published: (2020-07-01)

FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for High-Performance Processor
by: Hajkazemi, Mohammad Hossein
Published: (2013)

The Low Power Design Model Based on RNS-FIR
by: Zijun Zhang, et al.
Published: (2013-08-01)

Real-time fault tolerant full adder design for critical applications
by: Pankaj Kumar, et al.
Published: (2016-09-01)

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization
by: Muhammad Ali Akbar, et al.
Published: (2020-01-01)

Power Estimation of High Speed Bit-Parallel Adders
by: Åslund, Anders
Published: (2004)

The status of and some notes on the Gaboon adder <i>Bitis gabonica</i> in northern KwaZulu/Natal, South Africa and southern Mozambique
by: R. Kyle
Published: (2003-12-01)

Modified 32-Bit Shift-Add Multiplier Design for Low Power Application
by: R. Pinto
Published: (2020-12-01)

Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits
by: Gharajeh Mohammad Samadi, et al.
Published: (2020-01-01)

Latency Optimized Asynchronous Early Output Ripple Carry Adder Based on Delay-insensitive Dual-rail Data Encoding
by: Balasubramanian, P, et al.
Published: (2019)

Synthesis of parallel adders from if-decision diagrams
by: A. A. Prihozhy
Published: (2020-08-01)

PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER
by: M. AntoBennet, et al.
Published: (2017-12-01)

Ultracompact all-optical full-adder and half-adder based on nonlinear plasmonic nanocavities
by: Xie Jingya, et al.
Published: (2017-06-01)

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer
by: Ali, S.H, et al.
Published: (2021)

Redistribution of Signals Power in Multipath System of Radio Communication
by: W. I. Kaganov, et al.
Published: (2019-08-01)

Design and Simulation of a Nanoscale Threshold-Logic Multiplier
by: Mawahib Hussein Sulieman, et al.
Published: (2019-05-01)

In Dogs With a European Adder Bite, Does the Use of Antivenom With Supportive Treatment Compared to Supportive Treatment Alone Improve Time to Recovery?
by: Lindsay Hodgson, et al.
Published: (2017-11-01)

Ensuring the Data Integrity in Infocommunication Systems
by: Frolov, A., et al.
Published: (2022)

Asynchronous carry select adders
by: P. Balasubramanian
Published: (2017-06-01)

A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing
by: Allwin, Priscilla Sharon
Published: (2019)

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
by: Fasih Ud Din Farrukh, et al.
Published: (2020-01-01)

Cannot write session to /tmp/vufind_sessions/sess_s9cmgve8htau4rg6gjrr0usovj