Improving Packet Processing Efficiency on Multi-core Architectures with Single Input Queue
Generic purpose multi-core PC architectures are facing performance challenges of high rate packet reception on gigabit per second and higher speed network interfaces. In order to assign a CPU core to a networking softIRQ, the single input queue design of the low-level packet processing subsyste...
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| Format: | Article |
| Language: | English |
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UT Press Publishing House
2012-06-01
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| Series: | Carpathian Journal of Electronic and Computer Engineering |
| Online Access: | http://cjece.ubm.ro/vol/5-2012/9_Orosz.pdf |