A Programmable, Scalable-Throughput Interleaver

<p/> <p>The interleaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. M...

Full description

Bibliographic Details
Main Authors: Rijshouwer EJC, van Berkel CH
Format: Article
Language:English
Published: SpringerOpen 2010-01-01
Series:EURASIP Journal on Wireless Communications and Networking
Online Access:http://jwcn.eurasipjournals.com/content/2010/513104
id doaj-80c2947812324f62b4211d969c8b0da2
record_format Article
spelling doaj-80c2947812324f62b4211d969c8b0da22020-11-24T21:52:51ZengSpringerOpenEURASIP Journal on Wireless Communications and Networking1687-14721687-14992010-01-0120101513104A Programmable, Scalable-Throughput InterleaverRijshouwer EJCvan Berkel CH<p/> <p>The interleaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multistream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleave data rates. Our interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts with an efficient resolution of bank conflicts. A wide range of cellular, connectivity, and broadcast interleavers have been mapped on this machine, with throughputs up to more than 0.5&#8201;Gsymbol/second. Although it was designed for channel interleaving, the application domain of the interleaver extends also to Turbo interleaving. The presented configuration of the architecture is designed as a part of a programmable outer receiver on a prototype board. It offers (near) universal programmability to enable the implementation of new interleavers. The interleaver measures 2.09&#8201;m<inline-formula> <graphic file="1687-1499-2010-513104-i1.gif"/></inline-formula> in 65&#8201;nm CMOS (including memories) and proves functional on silicon.</p>http://jwcn.eurasipjournals.com/content/2010/513104
collection DOAJ
language English
format Article
sources DOAJ
author Rijshouwer EJC
van Berkel CH
spellingShingle Rijshouwer EJC
van Berkel CH
A Programmable, Scalable-Throughput Interleaver
EURASIP Journal on Wireless Communications and Networking
author_facet Rijshouwer EJC
van Berkel CH
author_sort Rijshouwer EJC
title A Programmable, Scalable-Throughput Interleaver
title_short A Programmable, Scalable-Throughput Interleaver
title_full A Programmable, Scalable-Throughput Interleaver
title_fullStr A Programmable, Scalable-Throughput Interleaver
title_full_unstemmed A Programmable, Scalable-Throughput Interleaver
title_sort programmable, scalable-throughput interleaver
publisher SpringerOpen
series EURASIP Journal on Wireless Communications and Networking
issn 1687-1472
1687-1499
publishDate 2010-01-01
description <p/> <p>The interleaver stages of digital communication standards show a surprisingly large variation in throughput, state sizes, and permutation functions. Furthermore, data rates for 4G standards such as LTE-Advanced will exceed typical baseband clock frequencies of handheld devices. Multistream operation for Software Defined Radio and iterative decoding algorithms will call for ever higher interleave data rates. Our interleave machine is built around 8 single-port SRAM banks and can be programmed to generate up to 8 addresses every clock cycle. The scalable architecture combines SIMD and VLIW concepts with an efficient resolution of bank conflicts. A wide range of cellular, connectivity, and broadcast interleavers have been mapped on this machine, with throughputs up to more than 0.5&#8201;Gsymbol/second. Although it was designed for channel interleaving, the application domain of the interleaver extends also to Turbo interleaving. The presented configuration of the architecture is designed as a part of a programmable outer receiver on a prototype board. It offers (near) universal programmability to enable the implementation of new interleavers. The interleaver measures 2.09&#8201;m<inline-formula> <graphic file="1687-1499-2010-513104-i1.gif"/></inline-formula> in 65&#8201;nm CMOS (including memories) and proves functional on silicon.</p>
url http://jwcn.eurasipjournals.com/content/2010/513104
work_keys_str_mv AT rijshouwerejc aprogrammablescalablethroughputinterleaver
AT vanberkelch aprogrammablescalablethroughputinterleaver
AT rijshouwerejc programmablescalablethroughputinterleaver
AT vanberkelch programmablescalablethroughputinterleaver
_version_ 1725874450460573696