Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime
The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell...
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Electronics and Telecommunications Research Institute (ETRI)
2019-10-01
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| Online Access: | https://doi.org/10.4218/etrij.2018-0281 |
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doaj-805c2fc8530d4402b99abdd3f57d621a2020-11-25T02:24:28ZengElectronics and Telecommunications Research Institute (ETRI)ETRI Journal1225-64632019-10-0141682983710.4218/etrij.2018-028110.4218/etrij.2018-0281Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regimeEunseon YuBaegmo SonByungmin KamYong Sang JohSangjoon ParkWon‐Jun LeeJongwan JungSeongjae ChoThe p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (Lg) by examining a set of primary DC and AC parameters. The cutoff frequency (fT) and maximum oscillation frequency (fmax) of the proposed device were determined to be 440.0 and 753.9 GHz when Lg is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology.https://doi.org/10.4218/etrij.2018-0281cmos technologyhigh hole mobilitylow‐power high‐speed operationnanowire fetsige shell channelsub‐10‐nm logic technologyvalence‐band offset |
| collection |
DOAJ |
| language |
English |
| format |
Article |
| sources |
DOAJ |
| author |
Eunseon Yu Baegmo Son Byungmin Kam Yong Sang Joh Sangjoon Park Won‐Jun Lee Jongwan Jung Seongjae Cho |
| spellingShingle |
Eunseon Yu Baegmo Son Byungmin Kam Yong Sang Joh Sangjoon Park Won‐Jun Lee Jongwan Jung Seongjae Cho Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime ETRI Journal cmos technology high hole mobility low‐power high‐speed operation nanowire fet sige shell channel sub‐10‐nm logic technology valence‐band offset |
| author_facet |
Eunseon Yu Baegmo Son Byungmin Kam Yong Sang Joh Sangjoon Park Won‐Jun Lee Jongwan Jung Seongjae Cho |
| author_sort |
Eunseon Yu |
| title |
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime |
| title_short |
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime |
| title_full |
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime |
| title_fullStr |
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime |
| title_full_unstemmed |
Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime |
| title_sort |
si‐core/sige‐shell channel nanowire fet for sub‐10‐nm logic technology in the thz regime |
| publisher |
Electronics and Telecommunications Research Institute (ETRI) |
| series |
ETRI Journal |
| issn |
1225-6463 |
| publishDate |
2019-10-01 |
| description |
The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (Lg) by examining a set of primary DC and AC parameters. The cutoff frequency (fT) and maximum oscillation frequency (fmax) of the proposed device were determined to be 440.0 and 753.9 GHz when Lg is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology. |
| topic |
cmos technology high hole mobility low‐power high‐speed operation nanowire fet sige shell channel sub‐10‐nm logic technology valence‐band offset |
| url |
https://doi.org/10.4218/etrij.2018-0281 |
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