Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst...

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Main Authors: Reza Molavi, Hormoz Djahanshahi, Rod Zavari, Shahriar Mirabbasi
Format: Article
Language:English
Published: Hindawi Limited 2013-01-01
Series:Journal of Electrical and Computer Engineering
Online Access:http://dx.doi.org/10.1155/2013/364982
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spelling doaj-805204c0e68d47a8bb93b80f3817bd9d2021-07-02T02:36:42ZengHindawi LimitedJournal of Electrical and Computer Engineering2090-01472090-01552013-01-01201310.1155/2013/364982364982Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port IntegrationReza Molavi0Hormoz Djahanshahi1Rod Zavari2Shahriar Mirabbasi3PMC-Sierra, Burnaby, BC, V5A 4V7, CanadaPMC-Sierra, Burnaby, BC, V5A 4V7, CanadaPMC-Sierra, Burnaby, BC, V5A 4V7, CanadaUniversity of British Columbia, Vancouver, BC, V6T 1Z4, CanadaPhase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.http://dx.doi.org/10.1155/2013/364982
collection DOAJ
language English
format Article
sources DOAJ
author Reza Molavi
Hormoz Djahanshahi
Rod Zavari
Shahriar Mirabbasi
spellingShingle Reza Molavi
Hormoz Djahanshahi
Rod Zavari
Shahriar Mirabbasi
Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
Journal of Electrical and Computer Engineering
author_facet Reza Molavi
Hormoz Djahanshahi
Rod Zavari
Shahriar Mirabbasi
author_sort Reza Molavi
title Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
title_short Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
title_full Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
title_fullStr Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
title_full_unstemmed Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
title_sort low-jitter 0.1-to-5.8 ghz clock synthesizer for area-efficient per-port integration
publisher Hindawi Limited
series Journal of Electrical and Computer Engineering
issn 2090-0147
2090-0155
publishDate 2013-01-01
description Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.
url http://dx.doi.org/10.1155/2013/364982
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AT hormozdjahanshahi lowjitter01to58ghzclocksynthesizerforareaefficientperportintegration
AT rodzavari lowjitter01to58ghzclocksynthesizerforareaefficientperportintegration
AT shahriarmirabbasi lowjitter01to58ghzclocksynthesizerforareaefficientperportintegration
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