Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration
Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2013-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2013/364982 |
| Summary: | Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device. |
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| ISSN: | 2090-0147 2090-0155 |