| Summary: | Gate-all-around (GAA) field effect transistors (FETs) have appeared as one of the potential candidates for the electrostatic integrity required to reduce MOSFETs to minimum channel lengths. Meanwhile, the negative capacitance effect of ferroelectrics is known as a remarkable quality enhancer for MOSFETs in terms of reducing sub-threshold slope (SS), supply voltage, and power consumption by utilizing the gate voltage amplification phenomenon. In this work, combining these two phenomena we numerically design a cylindrical GAA NCFET where promising two-dimensional WSe<sub>2</sub> is used as a channel material. We have suggested a high-K dielectric consisting of a tri-layer HfO<sub>2</sub>/TiO<sub>2</sub>/HfO<sub>2</sub> and lead zirconate titanate (PZT) as a ferroelectric layer in the gate stacking. The extremely high <inline-formula> <tex-math notation="LaTeX">$I_{on}/I_{off}$ </tex-math></inline-formula> ratio on the order of 10<sup>12</sup> (six order higher than conventional FET), and the high on-state current of <inline-formula> <tex-math notation="LaTeX">$119~\mu \text{A}$ </tex-math></inline-formula> are the most remarkable findings of this device which exceeds all the earlier results. The integration of the NC effect utilizing a 20 nm PZT offers lowest <inline-formula> <tex-math notation="LaTeX">$SS$ </tex-math></inline-formula> of 18.9 mV/dec. Moreover, a large transconductance (<inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula>) of <inline-formula> <tex-math notation="LaTeX">$117~\mu \text{S}$ </tex-math></inline-formula> and a higher current cut-off frequency (<inline-formula> <tex-math notation="LaTeX">$f_{T}$ </tex-math></inline-formula>) of 335 GHz were reported from the output characteristics. These outcomes allude that the suggested device structure may create a new path for electronic devices; therefore, it can be used for high speed operation with low power consumption.
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