A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits

Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, whil...

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Main Authors: A. M. Mousavi, M. Khodadadi
Format: Article
Language:English
Published: Shahrood University of Technology 2018-07-01
Series:Journal of Artificial Intelligence and Data Mining
Subjects:
Online Access:http://jad.shahroodut.ac.ir/article_1059_fcefe618fe62de43246b018c7bd01c09.pdf
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spelling doaj-7acbc4acb8d54537989567437d8af0f62020-11-24T21:39:26ZengShahrood University of TechnologyJournal of Artificial Intelligence and Data Mining2322-52112322-44442018-07-016235536310.22044/jadm.2017.10591059A Fast and Self-Repairing Genetic Programming Designer for Logic CircuitsA. M. Mousavi0M. Khodadadi1Department of Electrical Engineering, Lorestan University, Khoramabad, Lorestan, Iran.Department of Electrical Engineering, Azad University, Arak Branch, Arak, Iran.Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, while being advantageous, evolutionary paradigms also have some limitations including: a) lack of confidence in reaching at the correct answer, b) long convergence time, and c) restriction on the tests performed with higher number of input variables. In this paper, we have implemented a genetic programming approach that given a Boolean function, outputs its equivalent circuit such that the truth table is covered and the minimum number of gates (and to some extent transistors and levels) are used. Furthermore, our implementation improves the aforementioned limitations by: Incorporating a self-repairing feature (improving limitation a); Efficient use of the conceivable coding space of the problem, which virtually brings about a kind of parallelism and improves the convergence time (improving limitation b). Moreover, we have applied our method to solve Boolean functions with higher number of inputs (improving limitation c). These issues are verified through multiple tests and the results are reported.http://jad.shahroodut.ac.ir/article_1059_fcefe618fe62de43246b018c7bd01c09.pdfGenetic ProgrammingLogical CircuitsDesign Optimization
collection DOAJ
language English
format Article
sources DOAJ
author A. M. Mousavi
M. Khodadadi
spellingShingle A. M. Mousavi
M. Khodadadi
A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
Journal of Artificial Intelligence and Data Mining
Genetic Programming
Logical Circuits
Design Optimization
author_facet A. M. Mousavi
M. Khodadadi
author_sort A. M. Mousavi
title A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
title_short A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
title_full A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
title_fullStr A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
title_full_unstemmed A Fast and Self-Repairing Genetic Programming Designer for Logic Circuits
title_sort fast and self-repairing genetic programming designer for logic circuits
publisher Shahrood University of Technology
series Journal of Artificial Intelligence and Data Mining
issn 2322-5211
2322-4444
publishDate 2018-07-01
description Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, while being advantageous, evolutionary paradigms also have some limitations including: a) lack of confidence in reaching at the correct answer, b) long convergence time, and c) restriction on the tests performed with higher number of input variables. In this paper, we have implemented a genetic programming approach that given a Boolean function, outputs its equivalent circuit such that the truth table is covered and the minimum number of gates (and to some extent transistors and levels) are used. Furthermore, our implementation improves the aforementioned limitations by: Incorporating a self-repairing feature (improving limitation a); Efficient use of the conceivable coding space of the problem, which virtually brings about a kind of parallelism and improves the convergence time (improving limitation b). Moreover, we have applied our method to solve Boolean functions with higher number of inputs (improving limitation c). These issues are verified through multiple tests and the results are reported.
topic Genetic Programming
Logical Circuits
Design Optimization
url http://jad.shahroodut.ac.ir/article_1059_fcefe618fe62de43246b018c7bd01c09.pdf
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