A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion no...

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Main Authors: Chuangze Li, Benguang Han, Jie He, Zhongjie Guo, Longsheng Wu
Format: Article
Language:English
Published: MDPI AG 2020-02-01
Series:Sensors
Subjects:
Online Access:https://www.mdpi.com/1424-8220/20/4/1046
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spelling doaj-79bdc9d38eeb4395b0628a65ab793c792020-11-25T02:37:02ZengMDPI AGSensors1424-82202020-02-01204104610.3390/s20041046s20041046A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing TechniqueChuangze Li0Benguang Han1Jie He2Zhongjie Guo3Longsheng Wu4Xi’an Microelectronic Technology Institute, No. 198 Taibai South Road, Yanta District, Xi’an 710071, ChinaSchool of Microelectronics, Xi dian University, No. 2 Taibai South Road, Yanta District, Xi’an 710071, ChinaXi’an Microelectronic Technology Institute, No. 198 Taibai South Road, Yanta District, Xi’an 710071, ChinaDepartment of Electronic Engineering, Xi’an University of Technology, No. 5, Jinhua South Road, Beilin District, Xi’an 710054, ChinaXi’an Microelectronic Technology Institute, No. 198 Taibai South Road, Yanta District, Xi’an 710071, ChinaFor a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.https://www.mdpi.com/1424-8220/20/4/1046cmos image sensorlinearityadaptive nonlinear rampfully differential pipelinedouble auto-zeroinghigh frameratefixed pattern noisefloating diffusionreadout schemeramp generator circuit
collection DOAJ
language English
format Article
sources DOAJ
author Chuangze Li
Benguang Han
Jie He
Zhongjie Guo
Longsheng Wu
spellingShingle Chuangze Li
Benguang Han
Jie He
Zhongjie Guo
Longsheng Wu
A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
Sensors
cmos image sensor
linearity
adaptive nonlinear ramp
fully differential pipeline
double auto-zeroing
high framerate
fixed pattern noise
floating diffusion
readout scheme
ramp generator circuit
author_facet Chuangze Li
Benguang Han
Jie He
Zhongjie Guo
Longsheng Wu
author_sort Chuangze Li
title A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
title_short A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
title_full A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
title_fullStr A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
title_full_unstemmed A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
title_sort highly linear cmos image sensor design based on an adaptive nonlinear ramp generator and fully differential pipeline sampling quantization with a double auto-zeroing technique
publisher MDPI AG
series Sensors
issn 1424-8220
publishDate 2020-02-01
description For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.
topic cmos image sensor
linearity
adaptive nonlinear ramp
fully differential pipeline
double auto-zeroing
high framerate
fixed pattern noise
floating diffusion
readout scheme
ramp generator circuit
url https://www.mdpi.com/1424-8220/20/4/1046
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