Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training

A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programmi...

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Main Authors: Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min
Format: Article
Language:English
Published: MDPI AG 2019-04-01
Series:Micromachines
Subjects:
Online Access:https://www.mdpi.com/2072-666X/10/4/245
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spelling doaj-7990c693bcb1469389918d26cc7380c42020-11-24T22:15:49ZengMDPI AGMicromachines2072-666X2019-04-0110424510.3390/mi10040245mi10040245Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant TrainingKhoa Van Pham0Tien Van Nguyen1Kyeong-Sik Min2School of Electrical Engineering, Kookmin University, Seoul 02707, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul 02707, South KoreaSchool of Electrical Engineering, Kookmin University, Seoul 02707, South KoreaA real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the memristors takes a very long time and consumes a large amount of power, because of the incremental behavior of memristor’s program-verify scheme for the fine-tuning of memristor’s conductance. To reduce the programming time and power, the partial gating scheme is proposed here to realize the partial training, where only some part of neurons are trained, which are more responsible in the recognition error. By retraining the part, rather than the entire crossbar, the programming time and power of memristor crossbar can be significantly reduced. The proposed scheme has been verified by CADENCE circuit simulation with the real memristor’s Verilog-A model. When compared to retraining the entire crossbar, the loss of recognition rate of the partial gating scheme has been estimated only as small as 2.5% and 2.9%, for the MNIST and CIFAR-10 datasets, respectively. However, the programming time and power can be saved by 86% and 89.5% than the 100% retraining, respectively.https://www.mdpi.com/2072-666X/10/4/245memristor crossbarpartial-gatedfast and power-efficient trainingdefect-tolerant training
collection DOAJ
language English
format Article
sources DOAJ
author Khoa Van Pham
Tien Van Nguyen
Kyeong-Sik Min
spellingShingle Khoa Van Pham
Tien Van Nguyen
Kyeong-Sik Min
Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
Micromachines
memristor crossbar
partial-gated
fast and power-efficient training
defect-tolerant training
author_facet Khoa Van Pham
Tien Van Nguyen
Kyeong-Sik Min
author_sort Khoa Van Pham
title Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
title_short Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
title_full Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
title_fullStr Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
title_full_unstemmed Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
title_sort partial-gated memristor crossbar for fast and power-efficient defect-tolerant training
publisher MDPI AG
series Micromachines
issn 2072-666X
publishDate 2019-04-01
description A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the memristors takes a very long time and consumes a large amount of power, because of the incremental behavior of memristor’s program-verify scheme for the fine-tuning of memristor’s conductance. To reduce the programming time and power, the partial gating scheme is proposed here to realize the partial training, where only some part of neurons are trained, which are more responsible in the recognition error. By retraining the part, rather than the entire crossbar, the programming time and power of memristor crossbar can be significantly reduced. The proposed scheme has been verified by CADENCE circuit simulation with the real memristor’s Verilog-A model. When compared to retraining the entire crossbar, the loss of recognition rate of the partial gating scheme has been estimated only as small as 2.5% and 2.9%, for the MNIST and CIFAR-10 datasets, respectively. However, the programming time and power can be saved by 86% and 89.5% than the 100% retraining, respectively.
topic memristor crossbar
partial-gated
fast and power-efficient training
defect-tolerant training
url https://www.mdpi.com/2072-666X/10/4/245
work_keys_str_mv AT khoavanpham partialgatedmemristorcrossbarforfastandpowerefficientdefecttoleranttraining
AT tienvannguyen partialgatedmemristorcrossbarforfastandpowerefficientdefecttoleranttraining
AT kyeongsikmin partialgatedmemristorcrossbarforfastandpowerefficientdefecttoleranttraining
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