A low power and high speed decoder design based on FPGA

A low power and high speed decoder design based on FPGA

In view of the complexity and inflexibility of the traditional encoding and decoding algorithms, this paper studies the forward propagation algorithm and structure of autoencoder neural networks. A low power consumption and high speed decoder system is proposed, using the autoencoder neural network...

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Bibliographic Details
Main Authors: Zhou Songjiang, Li Shengchen, Liu Ming
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2018-04-01
Series:Dianzi Jishu Yingyong
Subjects:
FPGA
decoder
autoencoder neural network
hardware implementation
high speed and low power consumption
Online Access:http://www.chinaaet.com/article/3000080146

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