Register Transfer Level Disparity generator with Stereo Vision
This tool can generate binary files for Xilinx FPGAs for “Stereo Vision-based disparity generation”. With related vendor tools this project can be ported to other types of FPGAs (such as Intel technology). Implementation is done using VHDL and Verilog hardware description languages. The tool is avai...
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| Format: | Article |
| Language: | English |
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Ubiquity Press
2021-07-01
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| Series: | Journal of Open Research Software |
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| Online Access: | https://openresearchsoftware.metajnl.com/articles/339 |