Multibit non-volatile memory based on WS2 transistor with engineered gate stack

Multibit non-volatile memory based on WS2 transistor with engineered gate stack

In this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enha...

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Main Authors: Xinyi Zhu, Longfei He, Yafen Yang, Kai Zhang, Hao Zhu, Lin Chen, Qingqing Sun
Format: Article
Language:English
Published: AIP Publishing LLC 2020-12-01
Series:AIP Advances
Online Access:http://dx.doi.org/10.1063/5.0037780
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spelling doaj-7128e059b4604b04b7cd5619ee4edb6d2021-01-05T15:00:06ZengAIP Publishing LLCAIP Advances2158-32262020-12-011012125124125124-510.1063/5.0037780Multibit non-volatile memory based on WS2 transistor with engineered gate stackXinyi Zhu0Longfei He1Yafen Yang2Kai Zhang3Hao Zhu4Lin Chen5Qingqing Sun6State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaState Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, People’s Republic of ChinaIn this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enhanced gate control over the WS2 channel and memory performance. The memory cells exhibited a sufficient memory window, fast programming and erasing speed, and excellent memory retention and endurance. Moreover, stable and discrete memory states have been achieved at small gate voltages. Such excellent memory characteristics originated from the intrinsic properties of the atomically thin WS2 material and the engineered gate stack with clean and robust interfaces. The better thermal stability, higher permittivity, deeper trap level, and relatively smaller bandgap of the Ta2O5 dielectric than other commonly used dielectrics such as SiO2 and Al2O3 also contribute to the memory reliability, which is very attractive for future information and data storage applications.http://dx.doi.org/10.1063/5.0037780
collection DOAJ
language English
format Article
sources DOAJ
author Xinyi Zhu
Longfei He
Yafen Yang
Kai Zhang
Hao Zhu
Lin Chen
Qingqing Sun
spellingShingle Xinyi Zhu
Longfei He
Yafen Yang
Kai Zhang
Hao Zhu
Lin Chen
Qingqing Sun
Multibit non-volatile memory based on WS2 transistor with engineered gate stack
AIP Advances
author_facet Xinyi Zhu
Longfei He
Yafen Yang
Kai Zhang
Hao Zhu
Lin Chen
Qingqing Sun
author_sort Xinyi Zhu
title Multibit non-volatile memory based on WS2 transistor with engineered gate stack
title_short Multibit non-volatile memory based on WS2 transistor with engineered gate stack
title_full Multibit non-volatile memory based on WS2 transistor with engineered gate stack
title_fullStr Multibit non-volatile memory based on WS2 transistor with engineered gate stack
title_full_unstemmed Multibit non-volatile memory based on WS2 transistor with engineered gate stack
title_sort multibit non-volatile memory based on ws2 transistor with engineered gate stack
publisher AIP Publishing LLC
series AIP Advances
issn 2158-3226
publishDate 2020-12-01
description In this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enhanced gate control over the WS2 channel and memory performance. The memory cells exhibited a sufficient memory window, fast programming and erasing speed, and excellent memory retention and endurance. Moreover, stable and discrete memory states have been achieved at small gate voltages. Such excellent memory characteristics originated from the intrinsic properties of the atomically thin WS2 material and the engineered gate stack with clean and robust interfaces. The better thermal stability, higher permittivity, deeper trap level, and relatively smaller bandgap of the Ta2O5 dielectric than other commonly used dielectrics such as SiO2 and Al2O3 also contribute to the memory reliability, which is very attractive for future information and data storage applications.
url http://dx.doi.org/10.1063/5.0037780
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AT yafenyang multibitnonvolatilememorybasedonws2transistorwithengineeredgatestack
AT kaizhang multibitnonvolatilememorybasedonws2transistorwithengineeredgatestack
AT haozhu multibitnonvolatilememorybasedonws2transistorwithengineeredgatestack
AT linchen multibitnonvolatilememorybasedonws2transistorwithengineeredgatestack
AT qingqingsun multibitnonvolatilememorybasedonws2transistorwithengineeredgatestack
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