| Summary: | In this work, a prototype of a charge-trapping memory device based on two-dimensional WS2 has been fabricated with an engineered gate stack for multilevel non-volatile memory application. A Si/SiO2/ITO/Al2O3/Ta2O5/Al2O3 stack has been successfully integrated with optimized layer thicknesses for enhanced gate control over the WS2 channel and memory performance. The memory cells exhibited a sufficient memory window, fast programming and erasing speed, and excellent memory retention and endurance. Moreover, stable and discrete memory states have been achieved at small gate voltages. Such excellent memory characteristics originated from the intrinsic properties of the atomically thin WS2 material and the engineered gate stack with clean and robust interfaces. The better thermal stability, higher permittivity, deeper trap level, and relatively smaller bandgap of the Ta2O5 dielectric than other commonly used dielectrics such as SiO2 and Al2O3 also contribute to the memory reliability, which is very attractive for future information and data storage applications.
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