Parallel logical control algorithms: verification and hardware implementation

Parallel logical control algorithms: verification and hardware implementation

A formal language (PRALU) has been proposed for representation of parallel algorithms for logical control. The paper contains a short description of its syntax and semantics, methods of checking PRALU-algorithms for correctness and methods for their hardware implementation. They include using sugges...

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Main Author: A.Zakrevskij
Format: Article
Language:English
Published: Institute of Mathematics and Computer Science of the Academy of Sciences of Moldova 1996-07-01
Series:Computer Science Journal of Moldova
Online Access:http://www.math.md/nrofdownloads.php?file=/files/csjm/v4-n1/v4-n1-(pp3-19).pdf
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spelling doaj-6f860ab854f04b3ba27303ca8b27a8fb2020-11-24T22:22:55ZengInstitute of Mathematics and Computer Science of the Academy of Sciences of MoldovaComputer Science Journal of Moldova1561-40421996-07-0141(10)319Parallel logical control algorithms: verification and hardware implementationA.Zakrevskij0Institute of Engineering Cybernetics, Surganova str. 6, 220012 Minsk, BelarusA formal language (PRALU) has been proposed for representation of parallel algorithms for logical control. The paper contains a short description of its syntax and semantics, methods of checking PRALU-algorithms for correctness and methods for their hardware implementation. They include using suggested parallel automata as a standard form of algorithms, coding their partial states by ternary vectors, and obtaining appropriate minimized systems of logical equations of the sequent type. The latter ones could be easily implemented by logic nets with matrix structure.http://www.math.md/nrofdownloads.php?file=/files/csjm/v4-n1/v4-n1-(pp3-19).pdf
collection DOAJ
language English
format Article
sources DOAJ
author A.Zakrevskij
spellingShingle A.Zakrevskij
Parallel logical control algorithms: verification and hardware implementation
Computer Science Journal of Moldova
author_facet A.Zakrevskij
author_sort A.Zakrevskij
title Parallel logical control algorithms: verification and hardware implementation
title_short Parallel logical control algorithms: verification and hardware implementation
title_full Parallel logical control algorithms: verification and hardware implementation
title_fullStr Parallel logical control algorithms: verification and hardware implementation
title_full_unstemmed Parallel logical control algorithms: verification and hardware implementation
title_sort parallel logical control algorithms: verification and hardware implementation
publisher Institute of Mathematics and Computer Science of the Academy of Sciences of Moldova
series Computer Science Journal of Moldova
issn 1561-4042
publishDate 1996-07-01
description A formal language (PRALU) has been proposed for representation of parallel algorithms for logical control. The paper contains a short description of its syntax and semantics, methods of checking PRALU-algorithms for correctness and methods for their hardware implementation. They include using suggested parallel automata as a standard form of algorithms, coding their partial states by ternary vectors, and obtaining appropriate minimized systems of logical equations of the sequent type. The latter ones could be easily implemented by logic nets with matrix structure.
url http://www.math.md/nrofdownloads.php?file=/files/csjm/v4-n1/v4-n1-(pp3-19).pdf
work_keys_str_mv AT azakrevskij parallellogicalcontrolalgorithmsverificationandhardwareimplementation
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