Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embed...

Full description

Bibliographic Details
Main Authors: John M. McNichols, Eric J. Balster, William F. Turri, Kerry L. Hill
Format: Article
Language:English
Published: Hindawi Limited 2013-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2013/140234
id doaj-6f2472704b154e98824717ca2af679c8
record_format Article
spelling doaj-6f2472704b154e98824717ca2af679c82020-11-24T22:39:10ZengHindawi LimitedInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/140234140234Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II EncodingJohn M. McNichols0Eric J. Balster1William F. Turri2Kerry L. Hill3Department of Electrical and Computer Engineering, University of Dayton, Kettering Laboratory, Room 341, 300 College Park, Dayton, OH 45469, USADepartment of Electrical and Computer Engineering, University of Dayton, Kettering Laboratory, Room 341, 300 College Park, Dayton, OH 45469, USAUniversity of Dayton Research Institute, 300 College Park, Dayton, OH 45469, USAAir Force Research Laboratory Sensors Directorate, Wright-Patterson Air Force Base, OH, USAThis paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.http://dx.doi.org/10.1155/2013/140234
collection DOAJ
language English
format Article
sources DOAJ
author John M. McNichols
Eric J. Balster
William F. Turri
Kerry L. Hill
spellingShingle John M. McNichols
Eric J. Balster
William F. Turri
Kerry L. Hill
Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
International Journal of Reconfigurable Computing
author_facet John M. McNichols
Eric J. Balster
William F. Turri
Kerry L. Hill
author_sort John M. McNichols
title Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
title_short Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
title_full Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
title_fullStr Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
title_full_unstemmed Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
title_sort design and implementation of an embedded nios ii system for jpeg2000 tier ii encoding
publisher Hindawi Limited
series International Journal of Reconfigurable Computing
issn 1687-7195
1687-7209
publishDate 2013-01-01
description This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.
url http://dx.doi.org/10.1155/2013/140234
work_keys_str_mv AT johnmmcnichols designandimplementationofanembeddedniosiisystemforjpeg2000tieriiencoding
AT ericjbalster designandimplementationofanembeddedniosiisystemforjpeg2000tieriiencoding
AT williamfturri designandimplementationofanembeddedniosiisystemforjpeg2000tieriiencoding
AT kerrylhill designandimplementationofanembeddedniosiisystemforjpeg2000tieriiencoding
_version_ 1725710555425013760

Similar Items