A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications
This paper proposes a new strategy to achieve balanced capacitor voltages in modular multilevel converters. Among the possible solutions, centralized arm control approaches are often adopted. These methods require a balancing technique based on a sorted list of the sub-modules according to their cap...
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doaj-6e58ecc85cc64a43b132b943fff6aa672020-11-24T20:47:30ZengMDPI AGElectronics2079-92922019-04-018444910.3390/electronics8040449electronics8040449A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC ApplicationsMattia Ricco0Laszlo Mathe1Manel Hammami2Francesco Lo Franco3Claudio Rossi4Remus Teodorescu5Department of Electrical, Electronic, and Information Engineering, University of Bologna, 40136 Bologna, ItalyEnergy Technology Department, Aalborg University, 9100 Aalborg, DenmarkDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, 40136 Bologna, ItalyDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, 40136 Bologna, ItalyDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, 40136 Bologna, ItalyEnergy Technology Department, Aalborg University, 9100 Aalborg, DenmarkThis paper proposes a new strategy to achieve balanced capacitor voltages in modular multilevel converters. Among the possible solutions, centralized arm control approaches are often adopted. These methods require a balancing technique based on a sorted list of the sub-modules according to their capacitor voltages. In order to achieve the aforementioned sorted list, different algorithms have been proposed in literature, such as: Sorting algorithms, max/min approaches, etc. However, the sorting algorithms require a long execution time, while the max/min approaches affect the converter dynamic response during faults. To overcome these issues, a new mapping strategy providing a quasi-sorted list is proposed in this paper. The suggested method is compared in simulation with both the classical bubble sorting algorithm, and the max/min method during both normal and faulty conditions. Moreover, the three methods have been implemented in a Xilinx Zynq-7000 System-on-Chip (SoC) device, in order to analyze the corresponding execution time and the required computational effort. Hardware-in-the-loop results are presented for demonstrating the superior performance of the proposed balancing strategy.https://www.mdpi.com/2079-9292/8/4/449modular multilevel converterscapacitor voltage balancingnearest level controlsorting strategy |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Mattia Ricco Laszlo Mathe Manel Hammami Francesco Lo Franco Claudio Rossi Remus Teodorescu |
spellingShingle |
Mattia Ricco Laszlo Mathe Manel Hammami Francesco Lo Franco Claudio Rossi Remus Teodorescu A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications Electronics modular multilevel converters capacitor voltage balancing nearest level control sorting strategy |
author_facet |
Mattia Ricco Laszlo Mathe Manel Hammami Francesco Lo Franco Claudio Rossi Remus Teodorescu |
author_sort |
Mattia Ricco |
title |
A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications |
title_short |
A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications |
title_full |
A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications |
title_fullStr |
A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications |
title_full_unstemmed |
A Capacitor Voltage Balancing Approach Based on Mapping Strategy for MMC Applications |
title_sort |
capacitor voltage balancing approach based on mapping strategy for mmc applications |
publisher |
MDPI AG |
series |
Electronics |
issn |
2079-9292 |
publishDate |
2019-04-01 |
description |
This paper proposes a new strategy to achieve balanced capacitor voltages in modular multilevel converters. Among the possible solutions, centralized arm control approaches are often adopted. These methods require a balancing technique based on a sorted list of the sub-modules according to their capacitor voltages. In order to achieve the aforementioned sorted list, different algorithms have been proposed in literature, such as: Sorting algorithms, max/min approaches, etc. However, the sorting algorithms require a long execution time, while the max/min approaches affect the converter dynamic response during faults. To overcome these issues, a new mapping strategy providing a quasi-sorted list is proposed in this paper. The suggested method is compared in simulation with both the classical bubble sorting algorithm, and the max/min method during both normal and faulty conditions. Moreover, the three methods have been implemented in a Xilinx Zynq-7000 System-on-Chip (SoC) device, in order to analyze the corresponding execution time and the required computational effort. Hardware-in-the-loop results are presented for demonstrating the superior performance of the proposed balancing strategy. |
topic |
modular multilevel converters capacitor voltage balancing nearest level control sorting strategy |
url |
https://www.mdpi.com/2079-9292/8/4/449 |
work_keys_str_mv |
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