High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

• Main Authors: Pavel Lyakhov, Maria Valueva, Georgii Valuev, Nikolai Nagornov
• Format: Article
• Language: English
• Published: IEEE 2020-01-01
• Series: IEEE Access
• Subjects: Digital signal processing; digital filter; modular Multiply-Accumulate unit; residue number system
• Online Access: https://ieeexplore.ieee.org/document/9261396/

The article proposes new modified Multiply-Accumulate (MAC) units called truncated MAC units and using residue number system (RNS) with moduli of a special form. The effectiveness of the proposed blocks is verified by hardware implementation of digital filtering. The paper presents a comparative theoretical analysis of the proposed approach using the RNS and the known methods using the conventional positional number system (PNS) and RNS. Moreover, in the paper, a hardware simulation on FPGA of digital filters using arithmetic of RNS is performed, and comparison with the known implementations are realized. It is shown that using proposed approach based on RNS makes it possible to increase the frequency of digital filters by about 4 times, and reduce the hardware costs by 3 times, in comparison with the use of the traditional positional number system. Comparison proposed method and known methods based on RNS shows that using proposed method allows to increase the frequency by about 2-6 times, and reduce the hardware costs by 1.5-5 times, with increasing power consumption by 23%. Obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC, etc.) for solving practical problems such as noise reduction, amplification and suppression of frequencies, interpolation, decimation, equalization, and many others.