Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method

In this study, a multiscale interface element method (MIEM) is developed to evaluate the interfacial peel and shear stress distributions in multilayer packaging structures. A newly developed polygon interface element contained many sides that could easily connect with many other polygon elements of...

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Main Authors: D. S. Liu, Y. W. Chen, C. Y. Tsai
Format: Article
Language:English
Published: Hindawi Limited 2018-01-01
Series:Mathematical Problems in Engineering
Online Access:http://dx.doi.org/10.1155/2018/4962498
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spelling doaj-6ba1cccbd62d4905b69fc3347b5805852020-11-25T01:49:58ZengHindawi LimitedMathematical Problems in Engineering1024-123X1563-51472018-01-01201810.1155/2018/49624984962498Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element MethodD. S. Liu0Y. W. Chen1C. Y. Tsai2Department of Mechanical Engineering and Advanced Institute of Manufacturing with High-Tech Innovations, National Chung Cheng University, Chiayi, TaiwanDepartment of Mechanical Engineering and Advanced Institute of Manufacturing with High-Tech Innovations, National Chung Cheng University, Chiayi, TaiwanDepartment of Mechanical Engineering and Advanced Institute of Manufacturing with High-Tech Innovations, National Chung Cheng University, Chiayi, TaiwanIn this study, a multiscale interface element method (MIEM) is developed to evaluate the interfacial peel and shear stress distributions in multilayer packaging structures. A newly developed polygon interface element contained many sides that could easily connect with many other polygon elements of much smaller scale. Simple model and less computation can obtain accurate stress distributions. After verification of the validity of the developed model, MIEM is applied to analyze thermal stress distribution of the chip scale package (CSP). In general, a good qualitative agreement has been observed between the various results. Moreover, MIEM can directly obtain the stress value at the interface, which is also one of the advantages of this method in dealing with multilayer structures.http://dx.doi.org/10.1155/2018/4962498
collection DOAJ
language English
format Article
sources DOAJ
author D. S. Liu
Y. W. Chen
C. Y. Tsai
spellingShingle D. S. Liu
Y. W. Chen
C. Y. Tsai
Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
Mathematical Problems in Engineering
author_facet D. S. Liu
Y. W. Chen
C. Y. Tsai
author_sort D. S. Liu
title Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
title_short Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
title_full Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
title_fullStr Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
title_full_unstemmed Thermal Stress Analysis of Chip Scale Packaging by Using Novel Multiscale Interface Element Method
title_sort thermal stress analysis of chip scale packaging by using novel multiscale interface element method
publisher Hindawi Limited
series Mathematical Problems in Engineering
issn 1024-123X
1563-5147
publishDate 2018-01-01
description In this study, a multiscale interface element method (MIEM) is developed to evaluate the interfacial peel and shear stress distributions in multilayer packaging structures. A newly developed polygon interface element contained many sides that could easily connect with many other polygon elements of much smaller scale. Simple model and less computation can obtain accurate stress distributions. After verification of the validity of the developed model, MIEM is applied to analyze thermal stress distribution of the chip scale package (CSP). In general, a good qualitative agreement has been observed between the various results. Moreover, MIEM can directly obtain the stress value at the interface, which is also one of the advantages of this method in dealing with multilayer structures.
url http://dx.doi.org/10.1155/2018/4962498
work_keys_str_mv AT dsliu thermalstressanalysisofchipscalepackagingbyusingnovelmultiscaleinterfaceelementmethod
AT ywchen thermalstressanalysisofchipscalepackagingbyusingnovelmultiscaleinterfaceelementmethod
AT cytsai thermalstressanalysisofchipscalepackagingbyusingnovelmultiscaleinterfaceelementmethod
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