| Summary: | Half-band filters are often used to achieve 2x extraction of digital signals during digital frequency conversion. For the non-multiplier implementation structure of the decimation filter, the shifting addition is often used instead of the multiplication operation to reduce the use of hardware resources, and the multi-phase decomposition technique is used to reduce the computational complexity of the overall filtering and reduce the overall power consumption of the hardware. Based on this, this paper further proposes a low power consumption implementation method. After verifying the function correctly through Modelsim software simulation, the comprehensive results of Design Complier software show that the proposed structure effectively reduces the power consumption and area of the half-band filter compared with the traditional general shift addition architecture.
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