| Summary: | Recent development on 3D flash memories largely promotes the wide application of Solid-State Drives (SSDs) by providing larger capacity from vertically-stacked layers. However, there exist speed variations across different layers because of manufacturing process variations or physical designs, which induces new challenges to fully explore the advantages of existing SSDs, e.g. the parallel structure. This paper investigates the effect of speed variation on the parallel performance of SSDs. To balance chips’ workloads, traditional method selects chips in a round-robin way. As chip queue time can be estimated by some main factors, the chip also can be chosen in a greedy way. However, because of the layer speed variation, queue time estimation model should be modified. This paper first establishes a new queue time estimation model with the awareness of the flash layer information. Then the model is used to estimate the chip queue time and to direct write requests into the chip with the least queue time. The key idea is to largely reduce queue time of each write, thus reducing the average SSD response time. Finally, this new request redirection method is evaluated on SSDsim with real world workloads. Experimental results show that our model can estimate the queue time more accurately and our new request redirection method can improve 8.3% of write queue time on average under the situation of 4 times speed variation among 16 layers.
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