Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing

An optimal design of semiconductor device and its process uniformity are critical factors affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible malfunctioning in semiconductor manufacturing. Two main tasks in optimal device design for semiconductor manufacturing,...

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Main Authors: Hyun-Chul Choi, Hyeok Yun, Jun-Sik Yoon, Rock-Hyun Baek
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9178720/
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spelling doaj-66bfa9ba6ceb4954ab5377095f9a2c962021-03-30T03:30:28ZengIEEEIEEE Access2169-35362020-01-01815935115937010.1109/ACCESS.2020.30199339178720Neural Approach for Modeling and Optimizing Si-MOSFET ManufacturingHyun-Chul Choi0https://orcid.org/0000-0002-3991-9466Hyeok Yun1https://orcid.org/0000-0003-4597-4389Jun-Sik Yoon2https://orcid.org/0000-0002-3132-4556Rock-Hyun Baek3https://orcid.org/0000-0002-6175-8101Department of Electronic Engineering, Yeungnam University, Gyeongsan, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology, Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology, Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology, Pohang, South KoreaAn optimal design of semiconductor device and its process uniformity are critical factors affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible malfunctioning in semiconductor manufacturing. Two main tasks in optimal device design for semiconductor manufacturing, i.e., parameter optimization and modeling, have been typically used either to characterize the devices by understanding how each parameter affects the device performances or to calibrate the parameters for SPICE circuit simulation. However, there still remains limitations in describing the relationship between all manufacturing parameters and figure-of-merits using several simple equations human experts can utilize. Even with the best model currently available, the optimal design of semiconductor device heavily relies on experiences of human experts and deals with time-consuming ad-hoc trials and non-holistic approaches. In this paper, we propose a new approach for data-based accurate electrical modeling of transistor, which is the most fundamental unit device of semiconductor, and fast optimization of its manufacturing parameters. Instead of the previous analytic approaches, finding finite equations derived from semiconductor physics, we utilize machine learning technique and neural networks to find appropriate modeling functions from data pairs of parameters and figure-of-merits. And for given desired figure-of-merits, we find optimal manufacturing parameters in holistic manner by using the learned functions of neural networks and fast gradient-based optimization method. Experimental results show that our neural-network-based-model directly estimate figure-of-merits with competitive accuracy and that our holistic optimization technique accurately and rapidly adapts the manufacturing parameters to meet desired figure-of-merits.https://ieeexplore.ieee.org/document/9178720/Transistorsemiconductor manufacturingholistic parameter optimizationmachine learningneural networksgradient descent method
collection DOAJ
language English
format Article
sources DOAJ
author Hyun-Chul Choi
Hyeok Yun
Jun-Sik Yoon
Rock-Hyun Baek
spellingShingle Hyun-Chul Choi
Hyeok Yun
Jun-Sik Yoon
Rock-Hyun Baek
Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
IEEE Access
Transistor
semiconductor manufacturing
holistic parameter optimization
machine learning
neural networks
gradient descent method
author_facet Hyun-Chul Choi
Hyeok Yun
Jun-Sik Yoon
Rock-Hyun Baek
author_sort Hyun-Chul Choi
title Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
title_short Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
title_full Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
title_fullStr Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
title_full_unstemmed Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing
title_sort neural approach for modeling and optimizing si-mosfet manufacturing
publisher IEEE
series IEEE Access
issn 2169-3536
publishDate 2020-01-01
description An optimal design of semiconductor device and its process uniformity are critical factors affecting desired figure-of-merits as well as reducing fabrication cost of fixing possible malfunctioning in semiconductor manufacturing. Two main tasks in optimal device design for semiconductor manufacturing, i.e., parameter optimization and modeling, have been typically used either to characterize the devices by understanding how each parameter affects the device performances or to calibrate the parameters for SPICE circuit simulation. However, there still remains limitations in describing the relationship between all manufacturing parameters and figure-of-merits using several simple equations human experts can utilize. Even with the best model currently available, the optimal design of semiconductor device heavily relies on experiences of human experts and deals with time-consuming ad-hoc trials and non-holistic approaches. In this paper, we propose a new approach for data-based accurate electrical modeling of transistor, which is the most fundamental unit device of semiconductor, and fast optimization of its manufacturing parameters. Instead of the previous analytic approaches, finding finite equations derived from semiconductor physics, we utilize machine learning technique and neural networks to find appropriate modeling functions from data pairs of parameters and figure-of-merits. And for given desired figure-of-merits, we find optimal manufacturing parameters in holistic manner by using the learned functions of neural networks and fast gradient-based optimization method. Experimental results show that our neural-network-based-model directly estimate figure-of-merits with competitive accuracy and that our holistic optimization technique accurately and rapidly adapts the manufacturing parameters to meet desired figure-of-merits.
topic Transistor
semiconductor manufacturing
holistic parameter optimization
machine learning
neural networks
gradient descent method
url https://ieeexplore.ieee.org/document/9178720/
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AT hyeokyun neuralapproachformodelingandoptimizingsimosfetmanufacturing
AT junsikyoon neuralapproachformodelingandoptimizingsimosfetmanufacturing
AT rockhyunbaek neuralapproachformodelingandoptimizingsimosfetmanufacturing
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