Performing Cache Timing Attacks from the Reconfigurable Part of a Heterogeneous SoC—An Experimental Study

• Main Authors: Lilian Bossuet, El Mehdi Benhani
• Format: Article
• Language: English
• Published: MDPI AG 2021-07-01
• Series: Applied Sciences
• Subjects: cache timing analysis; side-channel attack; covert channel; heterogeneous SoC security
• Online Access: https://www.mdpi.com/2076-3417/11/14/6662
• ISSN: 2076-3417

Cache attacks are widespread on microprocessors and multi-processor system-on-chips but have not yet spread to heterogeneous systems-on-chip such as SoC-FPGA that are found in increasing numbers of applications on servers or in the cloud. This type of SoC has two parts: a processing system that includes hard components and ARM processor cores and a programmable logic part that includes logic gates to be used to implement custom designs. The two parts communicate via memory-mapped interfaces. One of these interfaces is the accelerator coherency port that provides optional cache coherency between the two parts. In this paper, we discuss the practicability and potential threat of inside-SoC cache attacks using the cache coherency mechanism of a complex heterogeneous SoC-FPGA. We provide proof of two cache timing attacks <i>Flush+Reload</i> and <i>Evict+Time</i> when SoC-FPGA is targeted, and proof of hidden communication using a cache-based covert channel. The heterogeneous SoC-FPGA Xilinx Zynq-7010 is used as an experimental target.