Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces

We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al...

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Main Authors: Tsung-En Lee, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Format: Article
Language:English
Published: AIP Publishing LLC 2021-08-01
Series:AIP Advances
Online Access:http://dx.doi.org/10.1063/5.0061573
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spelling doaj-61a47699e843425c9a788b872a3423032021-09-03T11:18:11ZengAIP Publishing LLCAIP Advances2158-32262021-08-01118085021085021-510.1063/5.0061573Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfacesTsung-En Lee0Kasidit Toprasertpong1Mitsuru Takenaka2Shinichi Takagi3Department of Electrical Engineering and Information Systems, The University of Tokyo, 2-11-16 Yayoi, Bunkyo, Tokyo 113-0032, JapanDepartment of Electrical Engineering and Information Systems, The University of Tokyo, 2-11-16 Yayoi, Bunkyo, Tokyo 113-0032, JapanDepartment of Electrical Engineering and Information Systems, The University of Tokyo, 2-11-16 Yayoi, Bunkyo, Tokyo 113-0032, JapanDepartment of Electrical Engineering and Information Systems, The University of Tokyo, 2-11-16 Yayoi, Bunkyo, Tokyo 113-0032, JapanWe study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.http://dx.doi.org/10.1063/5.0061573
collection DOAJ
language English
format Article
sources DOAJ
author Tsung-En Lee
Kasidit Toprasertpong
Mitsuru Takenaka
Shinichi Takagi
spellingShingle Tsung-En Lee
Kasidit Toprasertpong
Mitsuru Takenaka
Shinichi Takagi
Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
AIP Advances
author_facet Tsung-En Lee
Kasidit Toprasertpong
Mitsuru Takenaka
Shinichi Takagi
author_sort Tsung-En Lee
title Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
title_short Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
title_full Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
title_fullStr Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
title_full_unstemmed Re-examination of effects of ALD high-k materials on defect reduction in SiGe metal–oxide–semiconductor interfaces
title_sort re-examination of effects of ald high-k materials on defect reduction in sige metal–oxide–semiconductor interfaces
publisher AIP Publishing LLC
series AIP Advances
issn 2158-3226
publishDate 2021-08-01
description We study the impact of the atomic layer deposition high-k gate insulators on metal–oxide–semiconductor (MOS) interface properties of Si0.78Ge0.22 gate stacks with TiN gate electrodes and the physical origins of the reduction in MOS interface defects. The SiGe MOS interface properties of TiN/Y2O3, Al2O3, HfO2, and ZrO2 gate stacks are compared over a wide range of annealing temperatures. It is found that the lowest interface trap density (Dit) is obtained by TiN/Y2O3 stacks with post-metallization annealing (PMA) at 450 °C among the gate stacks with other gate insulators. Moreover, it is revealed that less amount of GeOx in the interfacial layer leads to lower Dit and that the Y2O3 stacks yield further reduction in Dit during PMA at 450 °C. These results can be explained by the reduction in distorted Ge–O bond densities in GeOx in ILs by scavenging and annealing effects during PMA and the suppression of Ge dangling bond generation by incorporating Y atoms into GeOx during PMA at 450 °C.
url http://dx.doi.org/10.1063/5.0061573
work_keys_str_mv AT tsungenlee reexaminationofeffectsofaldhighkmaterialsondefectreductioninsigemetaloxidesemiconductorinterfaces
AT kasidittoprasertpong reexaminationofeffectsofaldhighkmaterialsondefectreductioninsigemetaloxidesemiconductorinterfaces
AT mitsurutakenaka reexaminationofeffectsofaldhighkmaterialsondefectreductioninsigemetaloxidesemiconductorinterfaces
AT shinichitakagi reexaminationofeffectsofaldhighkmaterialsondefectreductioninsigemetaloxidesemiconductorinterfaces
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