FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing

• Main Authors: Torres-Huitzil César, Arias-Estrada Miguel
• Format: Article
• Language: English
• Published: SpringerOpen 2005-01-01
• Series: EURASIP Journal on Advances in Signal Processing
• Subjects: FPGA; configurable system; real time; window-based image processing; systolic array
• Online Access: http://dx.doi.org/10.1155/ASP.2005.1024
• ISSN: 1687-6172; 1687-6180

<p/> <p>Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of <inline-formula><graphic file="1687-6180-2005-264713-i1.gif"/></inline-formula> configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to <inline-formula><graphic file="1687-6180-2005-264713-i2.gif"/></inline-formula>, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of <inline-formula><graphic file="1687-6180-2005-264713-i3.gif"/></inline-formula> GOPs at a 60 MHz clock frequency and a processing time of <inline-formula><graphic file="1687-6180-2005-264713-i4.gif"/></inline-formula> milliseconds for <inline-formula><graphic file="1687-6180-2005-264713-i5.gif"/></inline-formula> generic window-based operators on <inline-formula><graphic file="1687-6180-2005-264713-i6.gif"/></inline-formula> gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.</p>