Formal Verification of Real-Time System Requirements
The methodology of system requirements verification presented in this paper is a proposition of a practical procedure for reducing some negatives of the specification of requirements. The main problem that is considered is to create a complete description of the system requirements without any negat...
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| Format: | Article |
| Language: | English |
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AGH University of Science and Technology Press
2000-01-01
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| Series: | Computer Science |
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| Online Access: | http://www.csci.agh.edu.pl/25/1/cs2000%2D05.pdf |
| Summary: | The methodology of system requirements verification presented in this paper is a proposition of a practical procedure for reducing some negatives of the specification of requirements. The main problem that is considered is to create a complete description of the system requirements without any negatives. Verification of the initially defined requirements is based on the coloured Petri nets. Those nets are useful for testing some properties of system requirements such as completeness, consistency and optimality. An example ofthe litt controller is presented. |
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| ISSN: | 1508-2806 |