MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture

MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture

Neural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structu...

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Bibliographic Details
Main Authors: Xuechen Zang, Shigetoshi Nakatake
Format: Article
Language:English
Published: MDPI AG 2021-07-01
Series:Applied Sciences
Subjects:
approximate computing
memory reconfigurable logic device
binary neural network
Online Access:https://www.mdpi.com/2076-3417/11/13/6213
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spelling doaj-5cd59f96805346d187b46ff5ae6216202021-07-15T15:31:05ZengMDPI AGApplied Sciences2076-34172021-07-01116213621310.3390/app11136213MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device ArchitectureXuechen Zang0Shigetoshi Nakatake1The Graduate School of Environmental Engineering, Hibikino Campus, The University of Kitakyushu, Kitakyushu 808-0135, Fukuoka, JapanThe Graduate School of Environmental Engineering, Hibikino Campus, The University of Kitakyushu, Kitakyushu 808-0135, Fukuoka, JapanNeural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structural features of a recently proposed memory-based programmable logic device, compare it with the standard structure, and test it on common datasets with full and binary precision, respectively. The experimental results reveal that the new structured network can provide almost consistent full-precision performance and binary-precision performance ranging from 61.0% to 78.8% after using sparser connections and about 50% reduction in the size of the weight matrix.https://www.mdpi.com/2076-3417/11/13/6213approximate computingmemory reconfigurable logic devicebinary neural network
collection DOAJ
language English
format Article
sources DOAJ
author Xuechen Zang
Shigetoshi Nakatake
spellingShingle Xuechen Zang
Shigetoshi Nakatake
MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
Applied Sciences
approximate computing
memory reconfigurable logic device
binary neural network
author_facet Xuechen Zang
Shigetoshi Nakatake
author_sort Xuechen Zang
title MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
title_short MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
title_full MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
title_fullStr MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
title_full_unstemmed MLUTNet: A Neural Network for Memory Based Reconfigurable Logic Device Architecture
title_sort mlutnet: a neural network for memory based reconfigurable logic device architecture
publisher MDPI AG
series Applied Sciences
issn 2076-3417
publishDate 2021-07-01
description Neural networks have been widely used and implemented on various hardware platforms, but high computational costs and low similarity of network structures relative to hardware structures are often obstacles to research. In this paper, we propose a novel neural network in combination with the structural features of a recently proposed memory-based programmable logic device, compare it with the standard structure, and test it on common datasets with full and binary precision, respectively. The experimental results reveal that the new structured network can provide almost consistent full-precision performance and binary-precision performance ranging from 61.0% to 78.8% after using sparser connections and about 50% reduction in the size of the weight matrix.
topic approximate computing
memory reconfigurable logic device
binary neural network
url https://www.mdpi.com/2076-3417/11/13/6213
work_keys_str_mv AT xuechenzang mlutnetaneuralnetworkformemorybasedreconfigurablelogicdevicearchitecture
AT shigetoshinakatake mlutnetaneuralnetworkformemorybasedreconfigurablelogicdevicearchitecture
_version_ 1721299900554018816

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