Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code
<p>A new novel method for area efficiency in FPGA implementation is presented. The method is realized <br />through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as <br />addition, subtraction and others. The design technique aim...
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| Format: | Article |
| Language: | English |
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Universitas Syiah Kuala
2012-10-01
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| Series: | Jurnal Rekayasa Elektrika |
| Online Access: | http://www.jurnal.unsyiah.ac.id/JRE/article/view/116 |
| Summary: | <p>A new novel method for area efficiency in FPGA implementation is presented. The method is realized <br />through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as <br />addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by <br />selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding <br />methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is <br />occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.</p> |
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| ISSN: | 1412-4785 2252-620X |