Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

• Main Authors: Kaipei Liu, Qing Huai, Liang Qin, Shu Zhu, Xiaobing Liao, Yuye Li, Hua Ding
• Format: Article
• Language: English
• Published: MDPI AG 2019-04-01
• Series: Applied Sciences
• Subjects: fault current-limiting circuit; DC circuit breaker; MMC-HVDC; fault protection
• Online Access: https://www.mdpi.com/2076-3417/9/8/1661

The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Specifically, the EFCLC consists of fault current-limiting inductance <inline-formula> <math display="inline"> <semantics> <mrow> <msub> <mi>L</mi> <mrow> <mi>F</mi> <mi>C</mi> <mi>L</mi> </mrow> </msub> </mrow> </semantics> </math> </inline-formula> and energy dissipation resistance <inline-formula> <math display="inline"> <semantics> <mrow> <msub> <mi>R</mi> <mrow> <mi>F</mi> <mi>C</mi> <mi>L</mi> </mrow> </msub> </mrow> </semantics> </math> </inline-formula> in parallel with surge arrestor. <inline-formula> <math display="inline"> <semantics> <mrow> <msub> <mi>L</mi> <mrow> <mi>F</mi> <mi>C</mi> <mi>L</mi> </mrow> </msub> </mrow> </semantics> </math> </inline-formula> reduces the fault current rising speed, together with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, <inline-formula> <math display="inline"> <semantics> <mrow> <msub> <mi>L</mi> <mrow> <mi>F</mi> <mi>C</mi> <mi>L</mi> </mrow> </msub> </mrow> </semantics> </math> </inline-formula> will be bypassed via parallel-connected thyristors after blocking converter to prevent the effect on fault interruption speed. <inline-formula> <math display="inline"> <semantics> <mrow> <msub> <mi>R</mi> <mrow> <mi>F</mi> <mi>C</mi> <mi>L</mi> </mrow> </msub> </mrow> </semantics> </math> </inline-formula> shares the stress on energy absorption device (metal oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisfied effortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its effectiveness is verified by simulation in RT-LAB and MATLAB software platforms.