Formal verification of a proof procedure for the description logic ALC
Description Logics (DLs) are a family of languages used for the representation and reasoning on the knowledge of an application domain, in a structured and formal manner. In order to achieve this objective, several provers, such as RACER and FaCT++, have been implemented, but these provers themselve...
Main Authors: | Martin Strecker, Mohamed Mezghiche, Mohamed Chaabani |
---|---|
Format: | Article |
Language: | English |
Published: |
Open Publishing Association
2013-07-01
|
Series: | Electronic Proceedings in Theoretical Computer Science |
Online Access: | http://arxiv.org/pdf/1307.8211v1 |
Similar Items
-
Logic Graphs for ALC, SHIF and SHOIN Description Logics
by: Nguyen Ngoc Than, et al.
Published: (2020-09-01) -
Converting ALC Connection Proofs into ALC Sequents
by: Eunice Palmeira, et al.
Published: (2019-08-01) -
Proof theoretical foundations for constructive Description Logic
by: Clément, Ian
Published: (2008) -
Formal Verification Methodologies for NULL Convention Logic Circuits
by: Le, Son Ngoc
Published: (2021) -
Proof of fault coverage for a formal protocol test procedure.
by: Randall, Michael Alan.
Published: (2012)