Methodology for the Simulation of the Variability of MOSFETs With Polycrystalline High-k Dielectrics Using CAFM Input Data

• Main Authors: A. Ruiz, C. Couso, N. Seoane, M. Porti, A. J. Garcia-Loureiro, M. Nafria
• Format: Article
• Language: English
• Published: IEEE 2021-01-01
• Series: IEEE Access
• Subjects: CAFM; high-k; MOSFET variability; polycrystalline dielectric; defect density; 3D device simulations
• Online Access: https://ieeexplore.ieee.org/document/9462835/

In this work, a simulation methodology, whose inputs are Conductive Atomic Force Microscope (CAFM) experimental data, is proposed to evaluate the impact of nanoscale variability sources related to the polycrystallization of high-k dielectrics (i.e., oxide thickness, t_ox, and charge density, <inline-formula> <tex-math notation="LaTeX">$\rho _{\mathrm {ox}}$ </tex-math></inline-formula>, fluctuations in the nanometer range) on the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) variability. To simulate this variability, a Thickness And Charge MAp Generator (TACMAG) has been developed and used in combination with an in-house-built 3D device simulator (VENDES). From CAFM experimental data (topography and current) obtained on a small area of a given polycrystalline dielectric, the TACMAG generates a high amount of t_ox and <inline-formula> <tex-math notation="LaTeX">$\rho _{\mathrm {ox}}$ </tex-math></inline-formula> configurations of the gate dielectric, with identical statistical characteristics to those experimentally measured. These dielectrics are then introduced into the device simulator, with which the impact of the t_ox and <inline-formula> <tex-math notation="LaTeX">$\rho _{\mathrm {ox}}$ </tex-math></inline-formula> fluctuations in the dielectric on the variability of MOSFETs (i.e., threshold voltage) is analyzed. Finally, the impact of different nanoscale parameters, such as the Grain size and Grain Boundaries depth (of polycrystalline dielectrics) on such variability has been evaluated.