Research on 1 GS/s，16-bit data acquisition system based on JESD204B
The paper adopts the architecture of "ADC+FPGA", designs and develops a 1 GS/s, 16-bit high-speed and high-precision data acquisition system(DAS), which realized the purpose of using a single channel to measure large dynamic range(DR>1 000) signals. The study uses two sysref modes, whic...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2021-04-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000130958 |