Coordinated Energy Management in Heterogeneous Processors
This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating...
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Series: | Scientific Programming |
Online Access: | http://dx.doi.org/10.3233/SPR-140380 |
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doaj-53b5f6f1545e4c6d8746b17add13694d2021-07-02T08:31:39ZengHindawi LimitedScientific Programming1058-92441875-919X2014-01-012229310810.3233/SPR-140380Coordinated Energy Management in Heterogeneous ProcessorsIndrani Paul0Vignesh Ravi1Srilatha Manne2Manish Arora3Sudhakar Yalamanchili4Advanced Micro Devices, Inc., USAAdvanced Micro Devices, Inc., USAAdvanced Micro Devices, Inc., USAAdvanced Micro Devices, Inc., USAGeorgia Institute of Technology, Atlanta, GA, USAThis paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2) product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.http://dx.doi.org/10.3233/SPR-140380 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Indrani Paul Vignesh Ravi Srilatha Manne Manish Arora Sudhakar Yalamanchili |
spellingShingle |
Indrani Paul Vignesh Ravi Srilatha Manne Manish Arora Sudhakar Yalamanchili Coordinated Energy Management in Heterogeneous Processors Scientific Programming |
author_facet |
Indrani Paul Vignesh Ravi Srilatha Manne Manish Arora Sudhakar Yalamanchili |
author_sort |
Indrani Paul |
title |
Coordinated Energy Management in Heterogeneous Processors |
title_short |
Coordinated Energy Management in Heterogeneous Processors |
title_full |
Coordinated Energy Management in Heterogeneous Processors |
title_fullStr |
Coordinated Energy Management in Heterogeneous Processors |
title_full_unstemmed |
Coordinated Energy Management in Heterogeneous Processors |
title_sort |
coordinated energy management in heterogeneous processors |
publisher |
Hindawi Limited |
series |
Scientific Programming |
issn |
1058-9244 1875-919X |
publishDate |
2014-01-01 |
description |
This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC) applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2) product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads. |
url |
http://dx.doi.org/10.3233/SPR-140380 |
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