New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been devel...

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Main Authors: Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta
Format: Article
Language:English
Published: Hindawi Limited 2011-01-01
Series:Journal of Electrical and Computer Engineering
Online Access:http://dx.doi.org/10.1155/2011/670508
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spelling doaj-52993827a0a34e6780aec150716d66192021-07-02T02:09:18ZengHindawi LimitedJournal of Electrical and Computer Engineering2090-01472090-01552011-01-01201110.1155/2011/670508670508New Low-Power Tristate Circuits in Positive Feedback Source-Coupled LogicKirti Gupta0Ranjana Sridhar1Jaya Chaudhary2Neeta Pandey3Maneesha Gupta4Electronics and Communication Department, Delhi Technological University, New Delhi, IndiaElectronics and Communication Department, Delhi Technological University, New Delhi, IndiaElectronics and Communication Department, Delhi Technological University, New Delhi, IndiaElectronics and Communication Department, Delhi Technological University, New Delhi, IndiaElectronics and Communication Division, Netaji Subhas Institute of Technology, New Delhi, IndiaTwo new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.http://dx.doi.org/10.1155/2011/670508
collection DOAJ
language English
format Article
sources DOAJ
author Kirti Gupta
Ranjana Sridhar
Jaya Chaudhary
Neeta Pandey
Maneesha Gupta
spellingShingle Kirti Gupta
Ranjana Sridhar
Jaya Chaudhary
Neeta Pandey
Maneesha Gupta
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
Journal of Electrical and Computer Engineering
author_facet Kirti Gupta
Ranjana Sridhar
Jaya Chaudhary
Neeta Pandey
Maneesha Gupta
author_sort Kirti Gupta
title New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
title_short New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
title_full New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
title_fullStr New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
title_full_unstemmed New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
title_sort new low-power tristate circuits in positive feedback source-coupled logic
publisher Hindawi Limited
series Journal of Electrical and Computer Engineering
issn 2090-0147
2090-0155
publishDate 2011-01-01
description Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.
url http://dx.doi.org/10.1155/2011/670508
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AT neetapandey newlowpowertristatecircuitsinpositivefeedbacksourcecoupledlogic
AT maneeshagupta newlowpowertristatecircuitsinpositivefeedbacksourcecoupledlogic
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