New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been devel...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2011-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2011/670508 |
| Summary: | Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits. |
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| ISSN: | 2090-0147 2090-0155 |