Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

• Main Authors: Mickael Fiorentino, Claude Thibeault, Yvon Savaria
• Format: Article
• Language: English
• Published: Wiley 2021-11-01
• Series: IET Computers & Digital Techniques
• Online Access: https://doi.org/10.1049/cdt2.12032
• ISSN: 1751-8601; 1751-861X

Abstract A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating.