Yield-improving test and routing circuits for a novel 3-D interconnect technology
This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMO...
| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2006-01-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/4/225/2006/ars-4-225-2006.pdf |
| Summary: | This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high. <P> The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production. |
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| ISSN: | 1684-9965 1684-9973 |