DLL-based 4-phase duty-cycle and phase correction circuit for high frequency clock tree
In high-speed data transmission applications such as double data rate memory and double sampling ADCs, clock generation and distribution circuits must provide the clocks with precise duty cycle of 50% and sufficient timing margin. The proposed DLL-based 4-phase duty-cycle and phase correction circui...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2016-01-01
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| Series: | MATEC Web of Conferences |
| Online Access: | http://dx.doi.org/10.1051/matecconf/20165412005 |