Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.

We report on scaling and timing tests of the SIESTA electronic structure code for ab initio molecular dynamics simulations using density-functional theory. The tests are performed on six large-scale supercomputers belonging to the PRACE Tier-0 network with four different architectures: Cray XE6, IBM...

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Main Author: Fabiano Corsetti
Format: Article
Language:English
Published: Public Library of Science (PLoS) 2014-01-01
Series:PLoS ONE
Online Access:http://europepmc.org/articles/PMC3991679?pdf=render
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spelling doaj-474ebccc66d841238954d5560d78c2622020-11-25T01:26:21ZengPublic Library of Science (PLoS)PLoS ONE1932-62032014-01-0194e9539010.1371/journal.pone.0095390Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.Fabiano CorsettiWe report on scaling and timing tests of the SIESTA electronic structure code for ab initio molecular dynamics simulations using density-functional theory. The tests are performed on six large-scale supercomputers belonging to the PRACE Tier-0 network with four different architectures: Cray XE6, IBM BlueGene/Q, BullX, and IBM iDataPlex. We employ a systematic strategy for simultaneously testing weak and strong scaling, and propose a measure which is independent of the range of number of cores on which the tests are performed to quantify strong scaling efficiency as a function of simulation size. We find an increase in efficiency with simulation size for all machines, with a qualitatively different curve depending on the supercomputer topology, and discuss the connection of this functional form with weak scaling behaviour. We also analyze the absolute timings obtained in our tests, showing the range of system sizes and cores favourable for different machines. Our results can be employed as a guide both for running SIESTA on parallel architectures, and for executing similar scaling tests of other electronic structure codes.http://europepmc.org/articles/PMC3991679?pdf=render
collection DOAJ
language English
format Article
sources DOAJ
author Fabiano Corsetti
spellingShingle Fabiano Corsetti
Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
PLoS ONE
author_facet Fabiano Corsetti
author_sort Fabiano Corsetti
title Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
title_short Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
title_full Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
title_fullStr Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
title_full_unstemmed Performance analysis of electronic structure codes on HPC systems: a case study of SIESTA.
title_sort performance analysis of electronic structure codes on hpc systems: a case study of siesta.
publisher Public Library of Science (PLoS)
series PLoS ONE
issn 1932-6203
publishDate 2014-01-01
description We report on scaling and timing tests of the SIESTA electronic structure code for ab initio molecular dynamics simulations using density-functional theory. The tests are performed on six large-scale supercomputers belonging to the PRACE Tier-0 network with four different architectures: Cray XE6, IBM BlueGene/Q, BullX, and IBM iDataPlex. We employ a systematic strategy for simultaneously testing weak and strong scaling, and propose a measure which is independent of the range of number of cores on which the tests are performed to quantify strong scaling efficiency as a function of simulation size. We find an increase in efficiency with simulation size for all machines, with a qualitatively different curve depending on the supercomputer topology, and discuss the connection of this functional form with weak scaling behaviour. We also analyze the absolute timings obtained in our tests, showing the range of system sizes and cores favourable for different machines. Our results can be employed as a guide both for running SIESTA on parallel architectures, and for executing similar scaling tests of other electronic structure codes.
url http://europepmc.org/articles/PMC3991679?pdf=render
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