Modified capacitor voltage balancing sorting algorithm for modular multilevel converter

• Main Authors: Jie Zhang, Jun Liu, Jiayu Liu, Wanliang Fang, Junxian Hou, Yifeng Dong
• Format: Article
• Language: English
• Published: Wiley 2019-01-01
• Series: The Journal of Engineering
• Subjects: HVDC power convertors; power grids; HVDC power transmission; power transmission control; computational complexity; PWM power convertors; capacitors; voltage control; power electronics; electric current control; power capacitors; power convertors; sorting; power system simulation; modified capacitor voltage; sorting algorithm; modular multilevel converter; large-scale sub-modules; simpler modulation; lower switching frequency; lower harmonic component; VSC–high voltage direct current transmission systems; sorting techniques; high switching frequency; power electronic devices; largest capacitor voltages; smallest module capacitor voltages; switching states; module voltage; capacitor voltage ripples; PSCAD/EMTDC; time-domain MMC-HVDC simulation
• Online Access: https://digital-library.theiet.org/content/journals/10.1049/joe.2018.8910

The modular multilevel converter (MMC) with large-scale sub-modules has the advantage of simpler modulation, lower switching frequency, and lower harmonic component, thus would be very promising in voltage source converter (VSC)–high voltage direct current transmission systems. Conventional capacitor voltage balancing algorithm suffers from insufficient grouping and sorting techniques. Therefore, it might result in excessive computation and high switching frequency of power electronic devices. To address the problem, a modified capacitor voltage balancing sorting algorithm is proposed in this paper. The proposed algorithm could avoid sorting all the module capacitor voltages by selecting only a certain number of the largest or smallest module capacitor voltages, and thus reduces time complexity greatly without losing control precision. Furthermore, the proposed algorithm focuses on the sub-modules whose capacitor voltage exceeds the limits, while the switching states of the other sub-modules are maintained to some degrees by employing the maintaining factor. Therefore, the switching frequency of the power electronic devices is further reduced. The performance of the proposed algorithm is evaluated through a time-domain MMC–HVDC simulation in PSCAD/EMTDC. Results show that the proposed algorithm is able to balance the module voltage with lower computation and reduce the switching frequency of power devices significantly, without noticeably increasing the capacitor voltage ripples.