FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves sig...

Full description

Bibliographic Details
Main Authors: Weian Yan, Weiqin Tong, Xiaoli Zhi
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Graph attention networks
model optimization
inference accelerating
field programmable gate array
heterogeneous computing
parallel computing
Online Access:https://ieeexplore.ieee.org/document/9195849/

Internet

https://ieeexplore.ieee.org/document/9195849/

Similar Items