Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process
This article details liquid level sensing utilizing interdigitated electrodes topology fabricated using CMOS process steps. Layer of silicon strip with multiple electrodes is employed for characterization of different liquids based on the principle of capacitance change and thereby relative dielectr...
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2015-03-01
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doaj-421d84a1b2e6491bbf89e1a766ccbab92020-11-24T22:01:50ZengIFSA Publishing, S.L.Sensors & Transducers2306-85151726-54792015-03-0118637984 Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS ProcessB. N. BALIGA0Kamaljeet SINGH1V. Kavitha2Navneet VERMA3M. M. NAYAK4K. Nagachenchaiah5V. K. Lakshmeesha6ISRO Satellite Centre, ISRO, DOS, HAL airport Road, Bangaluru-560078, India Semiconductor Laboratory, Sector 72, S.A.S Nagar, Chandigrah-160071, IndiaSemiconductor Laboratory, Sector 72, S.A.S Nagar, Chandigrah-160071, IndiaSemiconductor Laboratory, Sector 72, S.A.S Nagar, Chandigrah-160071, IndiaSemiconductor Laboratory, Sector 72, S.A.S Nagar, Chandigrah-160071, IndiaSemiconductor Laboratory, Sector 72, S.A.S Nagar, Chandigrah-160071, IndiaISRO Satellite Centre, ISRO, DOS, HAL airport Road, Bangaluru-560078, India This article details liquid level sensing utilizing interdigitated electrodes topology fabricated using CMOS process steps. Layer of silicon strip with multiple electrodes is employed for characterization of different liquids based on the principle of capacitance change and thereby relative dielectric constant. Optimization of oxide thickness is carried out to minimize substrate capacitance effect. Fabricated strip is assembled, packaged and integrated with electronic circuitry. This handy device can be employed to characterize various liquids along with level sensing of the storage tank with electronic display. Various liquid levels are characterized by employing the proposed structure. http://www.sensorsportal.com/HTML/DIGEST/march_2015/Vol_186/P_2626.pdfInter-digital topologyLiquid level sensorCMOS processsilicon substrate. |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
B. N. BALIGA Kamaljeet SINGH V. Kavitha Navneet VERMA M. M. NAYAK K. Nagachenchaiah V. K. Lakshmeesha |
spellingShingle |
B. N. BALIGA Kamaljeet SINGH V. Kavitha Navneet VERMA M. M. NAYAK K. Nagachenchaiah V. K. Lakshmeesha Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process Sensors & Transducers Inter-digital topology Liquid level sensor CMOS process silicon substrate. |
author_facet |
B. N. BALIGA Kamaljeet SINGH V. Kavitha Navneet VERMA M. M. NAYAK K. Nagachenchaiah V. K. Lakshmeesha |
author_sort |
B. N. BALIGA |
title |
Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process |
title_short |
Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process |
title_full |
Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process |
title_fullStr |
Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process |
title_full_unstemmed |
Liquid Level Sensing using Planar Inter-digitated Electrodes Employing CMOS Process |
title_sort |
liquid level sensing using planar inter-digitated electrodes employing cmos process |
publisher |
IFSA Publishing, S.L. |
series |
Sensors & Transducers |
issn |
2306-8515 1726-5479 |
publishDate |
2015-03-01 |
description |
This article details liquid level sensing utilizing interdigitated electrodes topology fabricated using CMOS process steps. Layer of silicon strip with multiple electrodes is employed for characterization of different liquids based on the principle of capacitance change and thereby relative dielectric constant. Optimization of oxide thickness is carried out to minimize substrate capacitance effect. Fabricated strip is assembled, packaged and integrated with electronic circuitry. This handy device can be employed to characterize various liquids along with level sensing of the storage tank with electronic display. Various liquid levels are characterized by employing the proposed structure.
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topic |
Inter-digital topology Liquid level sensor CMOS process silicon substrate. |
url |
http://www.sensorsportal.com/HTML/DIGEST/march_2015/Vol_186/P_2626.pdf |
work_keys_str_mv |
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1725838324286881792 |