User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing
Deep Learning techniques have been successfully applied to solve many Artificial Intelligence (AI) applications problems. However, owing to topologies with many hidden layers, Deep Neural Networks (DNNs) have high computational complexity, which makes their deployment difficult in contexts highly co...
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doaj-42114cba5463419081fd3d1312f7110a2021-06-28T23:00:40ZengIEEEIEEE Access2169-35362021-01-019891628918010.1109/ACCESS.2021.30901969458248User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge ComputingTarek Belabed0https://orcid.org/0000-0001-6356-0601Maria Gracielly F. Coutinho1https://orcid.org/0000-0001-8167-5568Marcelo A. C. Fernandes2https://orcid.org/0000-0001-7536-2506Carlos Valderrama Sakuyama3https://orcid.org/0000-0002-1693-6394Chokri Souani4https://orcid.org/0000-0002-8987-3582Université de Mons, Faculté Polytechnique, SEMi, Mons, BelgiumDepartment of Computer and Automation Engineering, Federal University of Rio Grande do Norte, Natal, BrazilDepartment of Computer and Automation Engineering, Federal University of Rio Grande do Norte, Natal, BrazilUniversité de Mons, Faculté Polytechnique, SEMi, Mons, BelgiumUniversité de Sousse, Institut Supérieur des Sciences Appliquées et de Technologie de Sousse, Sousse, TunisiaDeep Learning techniques have been successfully applied to solve many Artificial Intelligence (AI) applications problems. However, owing to topologies with many hidden layers, Deep Neural Networks (DNNs) have high computational complexity, which makes their deployment difficult in contexts highly constrained by requirements such as performance, real-time processing, or energy efficiency. Numerous hardware/software optimization techniques using GPUs, ASICs, and reconfigurable computing (i.e, FPGAs), have been proposed in the literature. With FPGAs, very specialized architectures have been developed to provide an optimal balance between high-speed and low power. However, when targeting edge computing, user requirements and hardware constraints must be efficiently met. Therefore, in this work, we only focus on reconfigurable embedded systems based on the Xilinx ZYNQ SoC and popular DNNs that can be implemented on Embedded Edge improving performance per watt while maintaining accuracy. In this context, we propose an automated framework for the implementation of hardware-accelerated DNN architectures. This framework provides an end-to-end solution that facilitates the efficient deployment of topologies on FPGAs by combining custom hardware scalability with optimization strategies. Cutting-edge comparisons and experimental results demonstrate that the architectures developed by our framework offer the best compromise between performance, energy consumption, and system costs. For instance, the low power (0.266W) DNN topologies generated for the MNIST database achieved a high throughput of 3,626 FPS.https://ieeexplore.ieee.org/document/9458248/Deep learningelectronic design automationedge computingFPGAlow power systems |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Tarek Belabed Maria Gracielly F. Coutinho Marcelo A. C. Fernandes Carlos Valderrama Sakuyama Chokri Souani |
spellingShingle |
Tarek Belabed Maria Gracielly F. Coutinho Marcelo A. C. Fernandes Carlos Valderrama Sakuyama Chokri Souani User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing IEEE Access Deep learning electronic design automation edge computing FPGA low power systems |
author_facet |
Tarek Belabed Maria Gracielly F. Coutinho Marcelo A. C. Fernandes Carlos Valderrama Sakuyama Chokri Souani |
author_sort |
Tarek Belabed |
title |
User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing |
title_short |
User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing |
title_full |
User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing |
title_fullStr |
User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing |
title_full_unstemmed |
User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing |
title_sort |
user driven fpga-based design automated framework of deep neural networks for low-power low-cost edge computing |
publisher |
IEEE |
series |
IEEE Access |
issn |
2169-3536 |
publishDate |
2021-01-01 |
description |
Deep Learning techniques have been successfully applied to solve many Artificial Intelligence (AI) applications problems. However, owing to topologies with many hidden layers, Deep Neural Networks (DNNs) have high computational complexity, which makes their deployment difficult in contexts highly constrained by requirements such as performance, real-time processing, or energy efficiency. Numerous hardware/software optimization techniques using GPUs, ASICs, and reconfigurable computing (i.e, FPGAs), have been proposed in the literature. With FPGAs, very specialized architectures have been developed to provide an optimal balance between high-speed and low power. However, when targeting edge computing, user requirements and hardware constraints must be efficiently met. Therefore, in this work, we only focus on reconfigurable embedded systems based on the Xilinx ZYNQ SoC and popular DNNs that can be implemented on Embedded Edge improving performance per watt while maintaining accuracy. In this context, we propose an automated framework for the implementation of hardware-accelerated DNN architectures. This framework provides an end-to-end solution that facilitates the efficient deployment of topologies on FPGAs by combining custom hardware scalability with optimization strategies. Cutting-edge comparisons and experimental results demonstrate that the architectures developed by our framework offer the best compromise between performance, energy consumption, and system costs. For instance, the low power (0.266W) DNN topologies generated for the MNIST database achieved a high throughput of 3,626 FPS. |
topic |
Deep learning electronic design automation edge computing FPGA low power systems |
url |
https://ieeexplore.ieee.org/document/9458248/ |
work_keys_str_mv |
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