A dual model node based optimization algorithm for simultaneous escape routing in PCBs
Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER i...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
PeerJ Inc.
2021-04-01
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| Series: | PeerJ Computer Science |
| Subjects: | |
| Online Access: | https://peerj.com/articles/cs-499.pdf |